512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Features
Mobile LPSDR SDRAM
MT48H32M16LF – 8 Meg x 16 x 4 Banks
MT48H16M32LF/LG – 4 Meg x 32 x 4 Banks
Features
Options
Marking
• VDD/VDDQ: 1.8V/1.8V
• Addressing
– Standard addressing option
– Reduced page size option1
• Configuration
– 32 Meg x 16 (8 Meg x 16 x 4
banks)
– 16 Meg x 32 (4 Meg x 32 x 4
banks)
• Plastic “green” packages
– 54-ball VFBGA (8mm x 8mm) 2
– 90-ball VFBGA (8mm x 13mm) 3
• Timing – cycle time
– 6ns at CL = 3
– 7.5ns at CL = 3
• Power
– Standard IDD2/IDD7
– Low-power IDD2/IDD71
• Operating temperature range
– Commercial (0˚C to +70˚C)
– Industrial (–40˚C to +85˚C)
– Automotive (–40˚C to +105˚C)
• Revision
• VDD/VDDQ = 1.7–1.95V
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal, pipelined operation; column address can
be changed every clock cycle
• Four internal banks for concurrent operation
• Programmable burst lengths: 1, 2, 4, 8, and continuous
• Auto precharge, includes concurrent auto precharge
• Auto refresh and self refresh modes
• LVTTL-compatible inputs and outputs
• On-chip temperature sensor to control self refresh
rate
• Partial-array self refresh (PASR)
• Deep power-down (DPD)
• Selectable output drive strength (DS)
• 64ms refresh period; 32ms for automotive temperature
Notes:
H
LF
LG
32M16
16M32
B4
B5
-6
-75
None
L
None
IT
AT
:C
1. Contact factory for availability.
2. Available only for x16 configuration.
3. Available only for x32 configuration.
Table 1: Configuration Addressing
32 Meg x 16
16 Meg x 32
16 Meg x 32 Reduced
Page Size Option1
Number of banks
4
4
4
Bank address balls
BA0, BA1
BA0, BA1
BA0, BA1
Row address balls
A[12:0]
A[12:0]
A[13:0]
Column address balls
Note: 1. Contact factory for availability.
A[9:0]
A[8:0]
A[7:0]
Architecture
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1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Features
Table 2: Key Timing Parameters
Clock Rate (MHz)
Access Time
Speed Grade
CL = 2
CL = 3
CL = 2
-6
104
166
8ns
5ns
-75
104
1. CL = CAS (READ) latency.
133
8ns
5.4ns
Note:
CL = 3
Figure 1: 512Mb Mobile LPSDR Part Numbering
MT
48
H 32M16 LF
B4
-75
IT
:C
Design Revision
Micron Technology
:C = Device generation
Product Family
Operating Temperature
48 = Mobile LPSDR SDRAM
Blank = Commercial (0°C to +70°C)
Operating Voltage
IT = Industrial (–40°C to +85°C)
H = 1.8V/1.8V
AT = Automotive (–40°C to +105°C)
Configuration
Low Power
32M16 = 32 Meg x 16
Blank = Standard IDD2/IDD7
16M32 = 16 Meg x 32
L = Low-power IDD2/IDD7
Addressing
Cycle Time
LF = Standard addressing
-6 = 6ns, tCK CL = 3
LG = Reduced page size
-75 = 7.5ns, tCK CL = 3
Package Codes
B4 = 8mm x 8mm, VFBGA, “green”
B5 = 8mm x 13mm, VFBGA, “green”
FBGA Part Marking Decoder
Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the
part number. Micron’s FBGA part marking decoder is available at www.micron.com/decoder.
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512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Features
Contents
Important Notes and Warnings ......................................................................................................................... 8
General Description ......................................................................................................................................... 9
Functional Block Diagram .............................................................................................................................. 10
Ball Assignments and Descriptions ................................................................................................................. 11
Package Dimensions ....................................................................................................................................... 14
Electrical Specifications .................................................................................................................................. 16
Absolute Maximum Ratings ........................................................................................................................ 16
Electrical Specifications – IDD Parameters ........................................................................................................ 18
Electrical Specifications – AC Operating Conditions ......................................................................................... 22
Output Drive Characteristics ........................................................................................................................... 25
Functional Description ................................................................................................................................... 28
Commands .................................................................................................................................................... 29
COMMAND INHIBIT .................................................................................................................................. 30
NO OPERATION (NOP) ............................................................................................................................... 30
LOAD MODE REGISTER (LMR) ................................................................................................................... 30
ACTIVE ...................................................................................................................................................... 30
READ ......................................................................................................................................................... 31
WRITE ....................................................................................................................................................... 32
PRECHARGE .............................................................................................................................................. 33
BURST TERMINATE ................................................................................................................................... 33
AUTO REFRESH ......................................................................................................................................... 33
SELF REFRESH ........................................................................................................................................... 34
DEEP POWER-DOWN ................................................................................................................................. 34
Truth Tables ................................................................................................................................................... 35
Initialization .................................................................................................................................................. 40
Mode Register ................................................................................................................................................ 42
Burst Length .............................................................................................................................................. 43
Burst Type .................................................................................................................................................. 43
CAS Latency ............................................................................................................................................... 45
Operating Mode ......................................................................................................................................... 45
Write Burst Mode ....................................................................................................................................... 45
Extended Mode Register ................................................................................................................................. 46
Temperature-Compensated Self Refresh ...................................................................................................... 46
Partial-Array Self Refresh ............................................................................................................................ 47
Output Drive Strength ................................................................................................................................ 47
Bank/Row Activation ...................................................................................................................................... 48
READ Operation ............................................................................................................................................. 49
WRITE Operation ........................................................................................................................................... 58
Burst Read/Single Write .............................................................................................................................. 65
PRECHARGE Operation .................................................................................................................................. 66
Auto Precharge ........................................................................................................................................... 66
AUTO REFRESH Operation ............................................................................................................................. 78
SELF REFRESH Operation ............................................................................................................................... 80
Power-Down .................................................................................................................................................. 82
Deep Power-Down ......................................................................................................................................... 83
Clock Suspend ............................................................................................................................................... 84
Revision History ............................................................................................................................................. 87
Rev. C, Production – 10/2018 ....................................................................................................................... 87
Rev. B, Production – 3/11 ............................................................................................................................ 87
Rev. A, Preliminary – 2/11 ........................................................................................................................... 87
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512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Features
List of Figures
Figure 1: 512Mb Mobile LPSDR Part Numbering ............................................................................................... 2
Figure 2: Functional Block Diagram ............................................................................................................... 10
Figure 3: 54-Ball VFBGA (Top View) ............................................................................................................... 11
Figure 4: 90-Ball VFBGA (Top View) ............................................................................................................... 12
Figure 5: 54-Ball VFBGA (8mm x 8mm) .......................................................................................................... 14
Figure 6: 90-Ball VFBGA (8mm x 13mm) ......................................................................................................... 15
Figure 7: Typical Self Refresh Current vs. Temperature .................................................................................... 21
Figure 8: ACTIVE Command .......................................................................................................................... 30
Figure 9: READ Command ............................................................................................................................. 31
Figure 10: WRITE Command ......................................................................................................................... 32
Figure 11: PRECHARGE Command ................................................................................................................ 33
Figure 12: Initialize and Load Mode Register .................................................................................................. 41
Figure 13: Mode Register Definition ............................................................................................................... 42
Figure 14: CAS Latency .................................................................................................................................. 45
Figure 15: Extended Mode Register Definition ................................................................................................ 46
Figure 16: Example: Meeting tRCD (MIN) When 2 < tRCD (MIN)/tCK < 3 .......................................................... 48
Figure 17: Consecutive READ Bursts .............................................................................................................. 50
Figure 18: Random READ Accesses ................................................................................................................ 51
Figure 19: READ-to-WRITE ............................................................................................................................ 52
Figure 20: READ-to-WRITE With Extra Clock Cycle ......................................................................................... 53
Figure 21: READ-to-PRECHARGE .................................................................................................................. 53
Figure 22: Terminating a READ Burst ............................................................................................................. 54
Figure 23: Alternating Bank Read Accesses ..................................................................................................... 55
Figure 24: READ Continuous Page Burst ......................................................................................................... 56
Figure 25: READ – DQM Operation ................................................................................................................ 57
Figure 26: WRITE Burst ................................................................................................................................. 58
Figure 27: WRITE-to-WRITE .......................................................................................................................... 59
Figure 28: Random WRITE Cycles .................................................................................................................. 60
Figure 29: WRITE-to-READ ............................................................................................................................ 60
Figure 30: WRITE-to-PRECHARGE ................................................................................................................. 61
Figure 31: Terminating a WRITE Burst ............................................................................................................ 62
Figure 32: Alternating Bank Write Accesses ..................................................................................................... 63
Figure 33: WRITE – Continuous Page Burst ..................................................................................................... 64
Figure 34: WRITE – DQM Operation ............................................................................................................... 65
Figure 35: READ With Auto Precharge Interrupted by a READ ......................................................................... 67
Figure 36: READ With Auto Precharge Interrupted by a WRITE ........................................................................ 68
Figure 37: READ With Auto Precharge ............................................................................................................ 69
Figure 38: READ Without Auto Precharge ....................................................................................................... 70
Figure 39: Single READ With Auto Precharge .................................................................................................. 71
Figure 40: Single READ Without Auto Precharge ............................................................................................. 72
Figure 41: WRITE With Auto Precharge Interrupted by a READ ........................................................................ 73
Figure 42: WRITE With Auto Precharge Interrupted by a WRITE ...................................................................... 73
Figure 43: WRITE With Auto Precharge ........................................................................................................... 74
Figure 44: WRITE Without Auto Precharge ..................................................................................................... 75
Figure 45: Single WRITE With Auto Precharge ................................................................................................. 76
Figure 46: Single WRITE Without Auto Precharge ............................................................................................ 77
Figure 47: Auto Refresh Mode ........................................................................................................................ 79
Figure 48: Self Refresh Mode .......................................................................................................................... 81
Figure 49: Power-Down Mode ........................................................................................................................ 82
Figure 50: Clock Suspend During WRITE Burst ............................................................................................... 84
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512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Features
Figure 51: Clock Suspend During READ Burst ................................................................................................. 85
Figure 52: Clock Suspend Mode ..................................................................................................................... 86
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512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Features
List of Tables
Table 1: Configuration Addressing ................................................................................................................... 1
Table 2: Key Timing Parameters ....................................................................................................................... 2
Table 3: VFBGA Ball Descriptions ................................................................................................................... 13
Table 4: Absolute Maximum Ratings .............................................................................................................. 16
Table 5: DC Electrical Characteristics and Operating Conditions ..................................................................... 16
Table 6: Capacitance ..................................................................................................................................... 17
Table 7: IDD Specifications and Conditions, –40˚C to 85˚C (x16) ....................................................................... 18
Table 8: IDD Specifications and Conditions, –40˚C to 85˚C (x32) ....................................................................... 18
Table 9: IDD Specifications and Conditions, , –40°C to +105°C (x16) .................................................................. 19
Table 10: IDD Specifications and Conditions, –40°C to +105°C (x32) .................................................................. 19
Table 11: IDD7 Specifications and Conditions (x16 and x32) ............................................................................. 20
Table 12: Electrical Characteristics and Recommended AC Operating Conditions ............................................ 22
Table 13: AC Functional Characteristics ......................................................................................................... 23
Table 14: Target Output Drive Characteristics (Full Strength) ........................................................................... 25
Table 15: Target Output Drive Characteristics (Three-Quarter Strength) .......................................................... 26
Table 16: Target Output Drive Characteristics (One-Half Strength) .................................................................. 27
Table 17: Truth Table – Commands and DQM Operation ................................................................................. 29
Table 18: Truth Table – Current State Bank n, Command to Bank n .................................................................. 35
Table 19: Truth Table – Current State Bank n, Command to Bank m ................................................................. 37
Table 20: Truth Table – CKE ........................................................................................................................... 39
Table 21: Burst Definition Table ..................................................................................................................... 44
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512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Features
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512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Important Notes and Warnings
Important Notes and Warnings
Micron Technology, Inc. ("Micron") reserves the right to make changes to information published in this document,
including without limitation specifications and product descriptions. This document supersedes and replaces all
information supplied prior to the publication hereof. You may not rely on any information set forth in this document if you obtain the product described herein from any unauthorized distributor or other source not authorized
by Micron.
Automotive Applications. Products are not designed or intended for use in automotive applications unless specifically designated by Micron as automotive-grade by their respective data sheets. Distributor and customer/distributor shall assume the sole risk and liability for and shall indemnify and hold Micron harmless against all claims,
costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of
product liability, personal injury, death, or property damage resulting directly or indirectly from any use of nonautomotive-grade products in automotive applications. Customer/distributor shall ensure that the terms and conditions of sale between customer/distributor and any customer of distributor/customer (1) state that Micron
products are not designed or intended for use in automotive applications unless specifically designated by Micron
as automotive-grade by their respective data sheets and (2) require such customer of distributor/customer to indemnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys'
fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage
resulting from any use of non-automotive-grade products in automotive applications.
Critical Applications. Products are not authorized for use in applications in which failure of the Micron component could result, directly or indirectly in death, personal injury, or severe property or environmental damage
("Critical Applications"). Customer must protect against death, personal injury, and severe property and environmental damage by incorporating safety design measures into customer's applications to ensure that failure of the
Micron component will not result in such harms. Should customer or distributor purchase, use, or sell any Micron
component for any critical application, customer and distributor shall indemnify and hold harmless Micron and
its subsidiaries, subcontractors, and affiliates and the directors, officers, and employees of each against all claims,
costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of
product liability, personal injury, or death arising in any way out of such critical application, whether or not Micron or its subsidiaries, subcontractors, or affiliates were negligent in the design, manufacture, or warning of the
Micron product.
Customer Responsibility. Customers are responsible for the design, manufacture, and operation of their systems,
applications, and products using Micron products. ALL SEMICONDUCTOR PRODUCTS HAVE INHERENT FAILURE RATES AND LIMITED USEFUL LIVES. IT IS THE CUSTOMER'S SOLE RESPONSIBILITY TO DETERMINE
WHETHER THE MICRON PRODUCT IS SUITABLE AND FIT FOR THE CUSTOMER'S SYSTEM, APPLICATION, OR
PRODUCT. Customers must ensure that adequate design, manufacturing, and operating safeguards are included
in customer's applications and products to eliminate the risk that personal injury, death, or severe property or environmental damages will result from failure of any semiconductor component.
Limited Warranty. In no event shall Micron be liable for any indirect, incidental, punitive, special or consequential
damages (including without limitation lost profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such damages are based on tort, warranty,
breach of contract or other legal theory, unless explicitly stated in a written agreement executed by Micron's duly
authorized representative.
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512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
General Description
General Description
The 512Mb Mobile LPSDR is a high-speed CMOS, dynamic random-access memory
containing 536,870,912-bits. It is internally configured as a quad-bank DRAM with a
synchronous interface (all signals are registered on the positive edge of the clock signal,
CLK). Each of the x16’s 134,217,728-bit banks is organized as 8192 rows by 1K columns
by 16 bits. Each of the x32’s 134,217,728-bit banks is organized as 8192 rows by 512 columns by 32 bits. In the reduced page size option, each of the x32’s 134,217,728-bit
banks is organized as 16,384 rows by 256 columns by 32 bits.
Mobile LPSDR offers substantial advances in DRAM operating performance, including
the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks in order to hide precharge time, and the capability to randomly change column addresses on each clock cycle during a burst access.
Note:
1. Throughout the data sheet, various figures and text refer to DQs as DQ. DQ should be
interpreted as any and all DQ collectively, unless specifically stated otherwise. Additionally, the x16 is divided into two bytes: the lower byte and the upper byte. For the lower
byte (DQ[7:0]), DQM refers to LDQM. For the upper byte (DQ[15:8]), DQM refers to
UDQM. The x32 is divided into four bytes. For DQ[7:0], DQM refers to DQM0. For
DQ[15:8], DQM refers to DQM1. For DQ[23:16], DQM refers to DQM2, and for
DQ[31:24], DQM refers to DQM3.
2. Complete functionality is described throughout the document; any page or diagram
may have been simplified to convey a topic and may not be inclusive of all requirements.
3. Any specific requirement takes precedence over a general statement.
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512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Functional Block Diagram
Functional Block Diagram
Figure 2: Functional Block Diagram
CKE
CLK
Control
logic
Command
decode
CS#
WE#
CAS#
RAS#
BA1
0
0
1
1
EXT mode
register
Mode register
Bank1
Refresh
counter
Bank0
row
address
latch
and
decoder
Row
address
MUX
Bank2
Address
BA0, BA1
Address
register
2
DQM
n
Data
output
register
n
n
DQ
Data
input
register
Column
decoder
Column/
address
counter/
latch
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Bank3
I/O gating
DQM mask logic
read data latch
write drivers
Bank
control
logic
Bank
0
1
2
3
Bank0
memory
array
Sense amplifiers
2
BA0
0
1
0
1
10
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512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Ball Assignments and Descriptions
Ball Assignments and Descriptions
Figure 3: 54-Ball VFBGA (Top View)
1
2
3
VSS
DQ15
DQ14
4
5
6
7
8
9
VSSQ
VDDQ
DQ0
VDD
DQ13
VDDQ
VSSQ
DQ2
DQ1
DQ12
DQ11
VSSQ
VDDQ
DQ4
DQ3
DQ10
DQ9
VDDQ
VSSQ
DQ6
DQ5
DQ8
DNU1
VSS
VDD
LDQM
DQ7
UDQM
CLK
CKE
CAS#
RAS#
WE#
A12
A11
A9
BA0
BA1
CS#
A8
A7
A6
A0
A1
A10
VSS
A5
A4
A3
A2
VDD
A
B
C
D
E
F
G
H
J
Note:
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1. The E2 pin must be connected to VSS, VSSQ, or left floating.
11
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512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Ball Assignments and Descriptions
Figure 4: 90-Ball VFBGA (Top View)
1
2
3
DQ26
DQ24
VSS
4
5
6
7
8
9
VDD
DQ23
DQ21
A
A
B
B
DQ28
VDDQ
VSSQ
VDDQ
VSSQ
DQ19
C
C
VSSQ
DQ27
DQ25
DQ22
DQ20
VDDQ
VSSQ
DQ29
DQ30
DQ17
DQ18
VDDQ
D
D
E
E
VDDQ
DQ31
NC
NC
DQ16
VSSQ
F
F
VSS
DQM3
A3
A2
DQM2
VDD
A4
A5
A6
A10
A0
A1
A7
A8
A12
A13
BA1
A11
G
G
H
H
J
J
CLK
CKE
A9
BA0
CS#
RAS#
DQM1
DNU1
NC
CAS#
WE#
DQM0
VDDQ
DQ8
VSS
VDD
DQ7
VSSQ
K
K
L
L
M
M
VSSQ
DQ10
DQ9
DQ6
DQ5
VDDQ
VSSQ
DQ12
DQ14
DQ1
DQ3
VDDQ
DQ11
VDDQ
VSSQ
VDDQ
VSSQ
DQ4
N
N
P
P
R
R
DQ13
Note:
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DQ15
VSS
VDD
DQ0
DQ2
1. The K2 pin must be connected to VSS, VSSQ, or left floating.
12
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512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Ball Assignments and Descriptions
Table 3: VFBGA Ball Descriptions
Symbol
Type
Description
CLK
Input
Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive
edge of CLK. CLK also increments the internal burst counter and controls the output registers.
CKE
Input
Clock enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. Deactivating the
clock provides precharge power-down and SELF REFRESH operation (all banks idle), active
power-down (row active in any bank), deep power-down (all banks idle), or CLOCK SUSPEND
operation (burst/access in progress). CKE is synchronous except after the device enters powerdown and self refresh modes, where CKE becomes asynchronous until after exiting the same
mode. The input buffers, including CLK, are disabled during power-down and self refresh
modes, providing low standby power.
CS#
Input
Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external
bank selection on systems with multiple banks. CS# is considered part of the command code.
CAS#, RAS#,
WE#
Input
Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being entered.
LDQM,
UDQM
(54-ball)
Input
Input/Output mask: DQM is sampled HIGH and is an input mask signal for write accesses and
an output enable signal for read accesses. Input data is masked during a WRITE cycle. The
output buffers are High-Z (two-clock latency) during a READ cycle. For the x16, LDQM corresponds to DQ[7:0] and UDQM corresponds to DQ[16:8]. For the x32, DQM0 corresponds to
DQ[7:0], DQM1 corresponds to DQ[15:8], DQM2 corresponds to DQ[23:16], and DQM3 corresponds to DQ[31:24]. DQM[3:0] (or LDQM and UDQM if x16) are considered same state when
referenced as DQM.
BA0, BA1
Input
Bank address input(s): BA0 and BA1 define to which bank the ACTIVE, READ, WRITE, or PRECHARGE command is being applied. BA0 and BA1 become “Don’t Care” when registering an
ALL BANK PRECHARGE (A10 HIGH).
A[13:0]
Input
Address inputs: Addresses are sampled during the ACTIVE command (row) and READ/WRITE
command [column); column address A[9:0] (x16); with A10 defining auto precharge] to select
one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine if all banks are to be precharged (A10 HIGH) or bank selected by BA0, BA1. The address inputs also provide the op-code during a LOAD MODE REGISTER command. The maximum address range is dependent upon configuration. Unused address pins become RFU.1
DQM[3:0]
(90-ball)
DQ[31:0]
I/O
VDDQ
Supply
DQ power: Provide isolated power to DQ for improved noise immunity.
Data input/output: Data bus.
VSSQ
Supply
DQ ground: Provide isolated ground to DQ for improved noise immunity.
VDD
Supply
Core power supply.
Ground.
VSS
Supply
DNU
–
Do not use: Must be grounded or left floating.
NC
–
Internally not connected. These balls can be left unconnected but it is recommended that
they be connected to VSS.
Note:
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1. Balls marked RFU may or may not be connected internally. These balls should not be
used. Contact the factory for details.
13
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512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Package Dimensions
Package Dimensions
Figure 5: 54-Ball VFBGA (8mm x 8mm)
Seating
plane
A
0.65 ±0.1
0.12 A
54X Ø0.45
Solder ball material:
SAC305 or SAC105.
Dimensions apply to
solder balls postreflow on Ø0.4 SMD
ball pads.
9
8
7
3
2
Ball A1 ID
1
Ball A1 ID
A
B
C
D
6.4 CTR
E
8 ±0.15
F
G
H
0.8 TYP
J
0.8 TYP
1 MAX
6.4 CTR
0.25 MIN
8 ±0.15
Note:
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1. All dimensions are in millimeters.
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Package Dimensions
Figure 6: 90-Ball VFBGA (8mm x 13mm)
Seating
plane
0.65 ±0.05
A
0.12 A
90X Ø0.45
Solder ball
material: SAC105
(98.5% Sn, 1% Ag,
0.5% Cu).
Dimensions apply
to solder balls postreflow on Ø0.4 SMD
ball pads.
Ball A1 ID
9 8 7
Ball A1 ID
3 2 1
A
B
C
D
E
F
G
H
J
11.2 CTR
13 ±0.1
K
L
M
N
P
R
0.8 TYP
0.8 TYP
1.0 MAX
6.4 CTR
0.275 MIN
8 ±0.1
Note:
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1. All dimensions are in millimeters.
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Electrical Specifications
Electrical Specifications
Absolute Maximum Ratings
Stresses greater than those listed may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
Table 4: Absolute Maximum Ratings
Voltage/Temperature
Symbol
Min
Max
Units
VDD/VDDQ
–0.5
2.4
V
Voltage on inputs, NC or I/O balls relative to VSS
VIN
–0.5
2.4
Storage temperature (plastic)
TSTG
–55
150
Voltage on VDD/VDDQ supply relative to VSS
Note:
1
˚C
1. VDD and VDDQ must be within 300mV of each other at all times. VDDQ must not exceed
VDD.
Table 5: DC Electrical Characteristics and Operating Conditions
Notes 1 and 2 apply to all parameters and conditions; VDD/VDDQ = 1.7–1.95V
Parameter/Condition
Symbol
Min
Max
Units
Notes
Supply voltage
VDD
1.7
1.95
V
I/O supply voltage
VDDQ
1.7
1.95
V
Input high voltage: Logic 1; All inputs
VIH
0.8 × VDDQ
VDDQ + 0.3
V
3
Input low voltage: Logic 0; All inputs
VIL
–0.3
+0.3
V
3
Output high voltage
VOH
0.9 × VDDQ
–
V
4
Output low voltage
VOL
–
0.2
V
4
II
–1.0
1.0
μA
Output leakage current: DQ are disabled; 0V ≤ VOUT ≤ VDDQ
IOZ
–1.5
1.5
μA
Operating temperature:
Industrial
TA
–40
85
˚C
Commercial
TA
0
70
˚C
Automotive
TA
–40
105
˚C
Input leakage current:
Any input 0V ≤ VIN ≤ VDD (All other balls not under test = 0V)
Notes:
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1. All voltages referenced to VSS.
2. A full initialization sequence is required before proper device operation is ensured.
3. VIH,max overshoot: VIH,max = VDDQ + 2V for a pulse width ≤3ns, and the pulse width cannot be greater than one- third of the cycle rate. VIL undershoot: VIL,min = –2V for a pulse
width ≤3ns.
4. IOUT = 4mA for full drive strength. Other drive strengths require appropriate scale.
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Electrical Specifications
Table 6: Capacitance
Note 1 applies to all parameters and conditions
Parameter
Symbol
Min
Max
Units
Input capacitance: CLK
CL1
2.0
5.0
pF
Input capacitance: All other input-only balls
CL2
2.0
5.0
pF
Input/output capacitance: DQ
CL0
2.5
6.0
pF
Note:
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1. This parameter is sampled. VDD, VDDQ = 1.8V; TA = 25˚C; ball under test biased at 0.9V,
f = 1 MHz.
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Electrical Specifications – IDD Parameters
Electrical Specifications – IDD Parameters
Table 7: IDD Specifications and Conditions, –40˚C to 85˚C (x16)
Note 1 applies to all parameters and conditions; VDD/VDDQ = 1.70–1.95V
Max
Parameter/Condition
Symbol
-6
-75
Units
Notes
Operating current: Active mode; Burst = 1; READ or WRITE; tRC = tRC
(MIN)
IDD1
90
80
mA
2, 3, 4
Standby current: Power-down mode; All banks idle; CKE = LOW
IDD2P
300
300
μA
5
Standby current: Non-power-down mode; All banks idle; CKE = HIGH
IDD2N
10
10
mA
3
Standby current: Active mode; CKE = LOW; CS# = HIGH; All banks active; No accesses in progress
IDD3P
5
5
mA
4, 6
Standby current: Active mode; CKE = HIGH; CS# = HIGH; All banks active after tRCD met; No accesses in progress
IDD3N
20
18
mA
3, 4, 6
Operating current: Burst mode; READ or WRITE; All banks active, half
of DQ toggling every cycle
IDD4
100
90
mA
2, 3, 4
95
95
mA
2, 3, 4, 6
Auto refresh current: CKE = HIGH; CS# = HIGH
tRFC
= 110ns
IDD5
tRFC
= 7.8125μs
IDD6
3
3
mA
2, 3, 4, 7
IZZ
10
10
μA
5, 8
Deep power-down
Table 8: IDD Specifications and Conditions, –40˚C to 85˚C (x32)
Note 1 applies to all parameters and conditions; VDD/VDDQ = 1.70–1.95V
Max
Parameter/Condition
Symbol
-6
-75
Units
Notes
IDD1
90
80
mA
2, 3, 4
Standby current: Power-down mode; All banks idle; CKE = LOW
IDD2P
300
300
μA
5
Standby current: Non-power-down mode; All banks idle; CKE =
HIGH
IDD2N
10
10
mA
3
Standby current: Active mode; CKE = LOW; CS# = HIGH; All banks
active; No accesses in progress
IDD3P
5
5
mA
4, 6
Standby current: Active mode; CKE = HIGH; CS# = HIGH; All banks
active after tRCD met; No accesses in progress
IDD3N
20
18
mA
3, 4, 6
Operating current: Burst mode; READ or WRITE; All banks active,
half DQ toggling every cycle
IDD4
105
95
mA
2, 3, 4
Operating current: Active mode; Burst = 1; READ or WRITE;
(MIN)
tRC
=
tRC
Auto refresh current: CKE = HIGH; CS# =
HIGH
tRFC
= 110ns
IDD5
95
95
mA
2, 3, 4, 6
tRFC
= 7.8125μs
IDD6
3
3
mA
2, 3, 4, 7
IZZ
10
10
μA
5, 8
Deep power-down
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Electrical Specifications – IDD Parameters
Table 9: IDD Specifications and Conditions, , –40°C to +105°C (x16)
Note 1 applies to all parameters and conditions; VDD/VDDQ = 1.70–1.95V
Max
Parameter/Condition
Symbol
-6
-75
Units
Notes
IDD1
90
80
mA
2, 3, 4
Standby current: Power-down mode; All banks idle; CKE = LOW
IDD2P
600
600
μA
5
Standby current: Non-power-down mode; All banks idle; CKE = HIGH
IDD2N
16
16
mA
3
Standby current: Active mode; CKE = LOW; CS# = HIGH; All banks active; No accesses in progress
IDD3P
6
6
mA
4, 6
Standby current: Active mode; CKE = HIGH; CS# = HIGH; All banks active after tRCD met; No accesses in progress
IDD3N
21
19
mA
3, 4, 6
Operating current: Burst mode; READ or WRITE; All banks active, half
of DQ toggling every cycle
IDD4
100
90
mA
2, 3, 4
Operating current: Active mode; Burst = 1; READ or WRITE;
(MIN)
Auto refresh current: CKE = HIGH; CS# = HIGH
tRC
=
tRC
tRFC
= 110ns
IDD5
95
95
mA
2, 3, 4, 6
tRFC
= 7.8125μs
IDD6
8
8
mA
2, 3, 4, 7
IZZ
15
15
μA
5, 8
Deep power-down
Table 10: IDD Specifications and Conditions, –40°C to +105°C (x32)
Note 1 applies to all parameters and conditions; VDD/VDDQ = 1.70–1.95V
Max
Parameter/Condition
Symbol
-6
-75
Units
Notes
Operating current: Active mode; Burst = 1; READ or WRITE; tRC =
tRC (MIN)
IDD1
90
80
mA
2, 3, 4
Standby current: Power-down mode; All banks idle; CKE = LOW
IDD2P
600
600
μA
5
Standby current: Non-power-down mode; All banks idle; CKE =
HIGH
IDD2N
16
16
mA
3
Standby current: Active mode; CKE = LOW; CS# = HIGH; All banks
active; No accesses in progress
IDD3P
6
6
mA
4, 6
Standby current: Active mode; CKE = HIGH; CS# = HIGH; All banks
active after tRCD met; No accesses in progress
IDD3N
21
19
mA
3, 4, 6
Operating current: Burst mode; READ or WRITE; All banks active,
half DQ toggling every cycle
IDD4
105
95
mA
2, 3, 4
95
95
mA
2, 3, 4, 6
Auto refresh current: CKE = HIGH; CS# =
HIGH
tRFC
= 110ns
IDD5
tRFC
= 7.8125μs
IDD6
8
8
mA
2, 3, 4, 7
IZZ
15
15
μA
5, 8
Deep power-down
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Electrical Specifications – IDD Parameters
Table 11: IDD7 Specifications and Conditions (x16 and x32)
Notes 1, 5, 9, and 10 apply to all parameters and conditions; VDD/VDDQ = 1.70–1.95V
Parameter/Condition
Symbol
Low Power
Self refresh
CKE = LOW;
Standard
Units
N/A11
N/A11
μA
Full array, 85˚C
TBD
700
μA
Full array, 45˚C
TBD
390
μA
Half array, 85˚C
TBD
520
μA
Half array, 45˚C
TBD
310
μA
1/4 array, 85˚C
TBD
430
μA
1/4 array, 45˚C
TBD
275
μA
1/8 array, 85˚C
TBD
430
μA
Full array, 105˚C
tCK
=
tCK
(MIN);
Address and control inputs are stable;
Data bus inputs are stable
Notes:
IDD7
1/8 array, 45˚C
TBD
275
μA
1/16 array, 85˚C
TBD
375
μA
1/16 array, 45˚C
TBD
250
μA
1. A full initialization sequence is required before proper device operation is ensured.
2. IDD is dependent on output loading and cycle rates. Specified values are obtained with
minimum cycle time and the outputs open.
3. The IDD current will increase or decrease proportionally according to the amount of frequency alteration for the test condition.
4. Address transitions average one transition every two clocks.
5. Measurement is taken 500ms after entering into this operating mode to allow tester
measuring unit settling time.
6. Other input signals are allowed to transition no more than once every two clocks and
are otherwise at valid VIH or VILlevels.
7. CKE is HIGH during REFRESH command period tRFC (MIN) else CKE is LOW.
8. Typical values at 25˚C (not a maximum value).
9. Enables on-die refresh and address counters.
10. Values for IDD7 85˚C full array and partial array are guaranteed for the entire temperature range. All other IDD7 values are estimated.
11. Self refresh is not supported for AT (85°C to 105°C) operation.
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Electrical Specifications – IDD Parameters
Figure 7: Typical Self Refresh Current vs. Temperature
500
Full
450
Half
400
Quarter
IDD6 (µA)
350
Eighth
300
Sixteenth
250
200
150
100
50
0
–40
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0
25
45
21
60
75
85
90
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Electrical Specifications – AC Operating Conditions
Electrical Specifications – AC Operating Conditions
Table 12: Electrical Characteristics and Recommended AC Operating Conditions
Notes 1–5 apply to all parameters and conditions
AC Characteristics
Parameter
Access time from CLK (positive edge)
CL = 3
-6
-75
Symbol
Min
Max
Min
Max
Unit
tAC
–
5
–
5.4
ns
–
8
–
8
1
–
1
–
CL = 2
Address hold time
tAH
Address setup time
tAS
1.5
–
1.5
–
ns
CLK high-level width
tCH
2.5
–
2.5
–
ns
CLK low-level width
tCL
2.5
–
2.5
–
ns
Clock cycle time
tCK
6
–
7.5
–
ns
CL = 3
CL = 2
ns
9.6
–
9.6
–
CKE hold time
tCKH
1
–
1
–
ns
CKE setup time
tCKS
1.5
–
1.5
–
ns
CS#, RAS#, CAS#, WE#, DQM hold time
tCMH
1
–
1
–
ns
CS#, RAS#, CAS#, WE#, DQM setup time
tCMS
1.5
–
1.5
–
ns
Data-in hold time
tDH
1
–
1
–
ns
Data-in setup time
tDS
1.5
–
1.5
–
ns
Data-out High-Z time
tHZ
–
5
–
5.4
ns
–
8
–
8
ns
Data-out Low-Z time
tLZ
1
–
1
–
ns
Data-out hold time (load)
tOH
2.5
–
2.5
–
ns
Data-out hold time (no load)
tOHn
1.8
–
1.8
–
ns
ACTIVE-to-PRECHARGE command
tRAS
42
120,000
45
120,000
ns
tRC
60
–
67.5
–
ns
ACTIVE-to-READ or WRITE delay
tRCD
18
–
19.2
–
ns
Refresh period (8192 rows)
tREF
–
64
–
64
ms
AUTO REFRESH period
tRFC
72
–
72
–
ns
tRP
18
–
19.2
–
ns
tRRD
2
–
2
–
tCK
tT
0.3
1.2
0.3
1.2
ns
CL = 3
CL = 2
ACTIVE-to-ACTIVE command period
PRECHARGE command period
ACTIVE bank a to ACTIVE bank b command
Transition time
Notes
6
7
8
9, 18
10
WRITE recovery time
tWR
15
–
15
–
ns
11
Exit SELF REFRESH-to-ACTIVE command
tXSR
120
–
120
–
ns
12
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Electrical Specifications – AC Operating Conditions
Table 13: AC Functional Characteristics
Notes 1–5 apply to all parameters and conditions
Parameter
Symbol
Last data-in to burst STOP command
tBDL
READ/WRITE command to READ/WRITE command
tCCD
Last data-in to new READ/WRITE command
tCDL
tCKED
CKE to clock disable or power-down entry mode
-6
-75
Units
Notes
1
1
tCK
13
1
1
tCK
13
1
tCK
14
1
tCK
14
15, 17
1
1
Data-in to ACTIVE command
tDAL
5
5
tCK
Data-in to PRECHARGE command
tDPL
2
2
tCK
16, 17
DQM to input data delay
tDQD
0
tCK
13
DQM to data mask during WRITEs
tDQM
0
tCK
13
DQM to data High-Z during READs
tDQZ
2
2
tCK
13
WRITE command to input data delay
tDWD
0
0
tCK
13
LOAD MODE REGISTER command to ACTIVE or REFRESH command
tMRD
2
2
tCK
CKE to clock enable or power-down exit mode
tPED
1
1
tCK
14
Last data-in to PRECHARGE command
tRDL
2
2
tCK
16, 17
tROH
3
3
tCK
13
2
tCK
Data-out High-Z from PRECHARGE command
CL = 3
CL = 2
Notes:
0
0
2
1. A full initialization sequence is required before proper device operation is ensured.
2. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (0˚C ≤ TA ≤ +70˚C standard temperature and –40˚C
≤ TA ≤ +85˚C industrial temperature) is ensured.
3. In addition to meeting the transition rate specification, the clock and CKE must transit
between VIH and VIL (or between VIL and VIH) in a monotonic manner.
4. Outputs measured for 1.8V at 0.9V with equivalent load:
Q
20pF
5.
6.
7.
8.
9.
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Test loads with full DQ driver strength. Performance will vary with actual system DQ bus
capacitive loading, termination, and programmed drive strength.
AC timing tests have VIL and VIH with timing referenced to VIH/2 = crossover point. If the
input transition time is longer than tTmax, then the timing is referenced at VIL,max and
VIH,min and no longer at the VIH/2 crossover point.
The clock frequency must remain constant (stable clock is defined as a signal cycling
within timing constraints specified for the clock ball) during access or precharge states
(READ, WRITE, including tWR, and PRECHARGE commands). CKE may be used to reduce
the data rate.
tHZ defines the time at which the output achieves the open circuit condition, it is not a
reference to VOH or VOL. The last valid data element will meet tOH before going High-Z.
DRAM devices should be evenly addressed when being accessed. Disproportionate accesses to a particular row address may result in reduction of the product lifetime.
This device requires 8192 AUTO REFRESH cycles every 64ms (tREF). Providing a distributed AUTO REFRESH command every 7.8125μs meets the refresh requirement and ensures that each row is refreshed. Alternatively, 8192 AUTO REFRESH commands can be
issued in a burst at the minimum cycle rate (tRFC), once every 64ms.
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Electrical Specifications – AC Operating Conditions
10. AC characteristics assume tT = 1ns. For command and address input slew rates
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